I am an RTL Design Engineer with 4 years of experience. I have worked with a licensed MIPS R6 core. My primary focus has been the development and maintenance of an IP block and its integration into an SoC. My skills include:

· Verifying simple digital blocks.
· Debugging test failures.
· RTL coding in Verilog and SystemVerilog.
· Developing scripts for EDA tool flows.
· Performing simulation and gate-level netlist synthesis.
· Using Linux, Bash, and Python in a professional environment.