SoC/IP Design Verification Engineer with experience in SystemVerilog and UVM-based verification methodologies for IP and SoC level environments. Skilled in developing reusable UVM testbenches, constrained-random verification, assertions (SVA), functional coverage, debugging, and protocol verification including AXI/APB/AHB. Familiar with simulation and debug tools such as QuestaSim, Synopsys VCS, and Verdi. Strong understanding of RTL design concepts, verification planning, coverage closure, and bug debugging across IP and SoC verification flows.